1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a trench type gate and a fabrication method therefor.
2. Description of the Related Art
As the size and capacity of integrated semiconductor devices increases, the need for a power controlling semiconductor device having a high breakdown voltage, a high current, and high switching characteristics also increases. Such a power controlling semiconductor device should consume less power in a normal operating state and be small.
One commonly used power controlling semiconductor device is a dynamic metal oxide semiconductor field effect transistor (DMOSFET) adopting a general planar diffusion technology. More recently, however, MOSFET devices having a trench type gate in which a semiconductor substrate is etched to a predetermined depth to form a trench have attracted the attention of the industry. The trench is filled with a gate polysilicon.
FIG. 1 is a sectional view of a conventional power MOSFET having a trench type gate. In FIG. 1, an N.sup.+ semiconductor substrate 10 is doped with a first conductive type impurity at a high concentration. An N.sup.- epitaxial layer 12 is formed on the substrate 10. A P.sup.- body region 14 is doped with a second conductive type impurity at a low concentration is formed on the N.sup.- epitaxial layer 12. An N.sup.+ source region 16 is formed on the P.sup.- body region 14. A gate insulating layer 18 is formed on the N.sup.+ source region 16. A gate 20 fills a trench (not shown). An interlayer dielectric (ILD) film 22 is formed on the gate insulating layer 18. A source electrode 24 is connected to the N.sup.+ source region 16. A gate electrode 26 is connected to the trench type gate 20.
In a conventional device, to reduce signal delay in the gate, the trench is filled with highly doped polysilicon after forming a trench in a semiconductor substrate. Alternatively, after filling the trench with undoped polysilicon, the polysilicon is doped by soaking the device in phosphoryl chloride (POCl.sub.3) solution or by implanting phosphorous (P) ions into the trench.
According to the conventional method for forming a gate, a large amount of ionized impurities e.g. phosphorous ions, working as positive charges, concentrate on the interface between a gate oxide layer and a polysilicon layer or in the gate oxide layer during its fabrication process. If a negative bias is applied under these conditions, leakage current in the gate oxide layer increases at a low voltage due to the ionized positive ions. This phenomenon occurs mostly in a power MOSFET adopting a thick gate oxide layer having a thickness greater than 300 A. This phenomenon becomes severe as the amount of ions accumulated in the gate oxide layer increases.
In particular, the oxide layer of a power MOSFET adopting a trench type gate thins at the corners of the trench. As a result, leakage current at low voltages increases when a negative bias is applied to a gate electrode thereby considerably lowering the reliability of the gate oxide layer.